3.3v, 150mhz, multi-output zero delay buffer cypress semiconductor corporation http://www.cypress.com document#: 38- 07091 rev. *b 12/26/2002 page 1 of 8 z9975 product features ? output frequency up to 150mhz ? supports power pc tm , and pentium tm processors ? 15 clock output: frequency configurable ? two reference clock inputs for dynamic toggling ? output tri-state control ? spread spectrum compatible ? 3.3v power supply ? industrial temp. range: -40c to +85c ? 52 pin tqfp package product description the z9975 is a low cost 3.3v zero delay clock driver for high speed signal buffering and redistribution. it provides the designer with the flexibility of selecting various output/input frequency ratios selected by fsela, fselb, fselc, fselfb(0:1), and vco_sel input settings. the z9975 integrates pll technology for zero delay propagation from input to output. the pll feedback is externally available for propagation delay tuning and divide ratio alternatives as per table 1. the z9975 has three banks of outputs with independent divider stages. these dividers allow the banks to have different frequencies as per table 2. tclk0 and tclk1 one are selectable input reference clocks and may be toggled dynamically during operation to provide modulation and phase shifting designs. this device includes a master reset signal that disables the outputs into tristate (hi-z) mode, and reset all internal digital circuitry (excluding the pll). an output enable, oe, input pin is available for shutting qa(0:4), qb(0:4), and qc(0:3) outputs in a low state. all outputs are held low with input clock turned off. feedback ratio selection table inputs outputs vco_sel1 vco_sel0 fselfb0 fselfb1 qfb 0000vco/8 0001vco/12 0010vco/16 0011vco/24 0100vco/16 0101vco/24 0110vco/32 0111vco/48 1000vco/4 1001vco/6 1010vco/8 1011vco/12 1100vco/8 1101vco/12 1110vco/16 1111vco/24 table 1 pin configuration vssa mr# oe fselb fselc pll_en fsela tclk_sel tclk0 tclk1 vco_sel1 vddi vdda vdda qa0 vssa qa1 vdda qa2 fselfb1 vssa qa3 vdda qa4 vssi fselfb0 qb0 vddb nc vssc qc3 vddc qc2 vssc qc1 vddc qc0 vssc vco_sel0 vssb qb1 vddb qb2 vssb qb3 vddb qb4 fb_in vssfb qfb vddfb nc 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 z9975
3.3v, 150mhz, multi-output zero delay buffer cypress semiconductor corporation http://www.cypress.com document#: 38- 07091 rev. *b 12/26/2002 page 2 of 8 z9975 block diagram fig.1 vdd vdd vdd vdd vdd 5 5 4 250k 1 0 0 1 divide by 1, 2 & 4 c /2 /4 divide by 2, 4 & 6 c /2 /4 /6 0 1 0 1 0 1 div. by 2 c /2 5 5 4 1 4 5 5 a b and gate a b y a b y 250k pll ref-in vco-out feedback 250k 250k 0 1 0 1 250k 250k 250k 250k 250k 250k 250k 250k 250k tclk0 tclk1 fb_in pll_en vco_sel0 qfb qa(0:4) qb(0:4) qc(0:3) mr# fsela tclk_sel oe fselc fselb fselfb1 fselfb0 reset# reset# reset# pllinit# y and gate and gate vco_sel1 vss /1 250k
3.3v, 150mhz, multi-output zero delay buffer cypress semiconductor corporation http://www.cypress.com document#: 38- 07091 rev. *b 12/26/2002 page 3 of 8 z9975 output frequency selection table (vco_sel1 = 0) inputs outputs vco_sel0 fsela fselb fselc qa(0:4) qb(0:4) qc(0:3) 0 0 0 0 vco/4 vco/4 vco/8 0 0 0 1 vco/4 vco/4 vco/12 0 0 1 0 vco/4 vco/8 vco/8 0 0 1 1 vco/4 vco/8 vco/12 0 1 0 0 vco/8 vco/4 vco/8 0 1 0 1 vco/8 vco/4 vco/12 0 1 1 0 vco/8 vco/8 vco/8 0 1 1 1 vco/8 vco/8 vco/12 1 0 0 0 vco/8 vco/8 vco/16 1 0 0 1 vco/8 vco/8 vco/24 1 0 1 0 vco/8 vco/16 vco/16 1 0 1 1 vco/8 vco/16 vco/24 1 1 0 0 vco/16 vco/8 vco/16 1 1 0 1 vco/16 vco/8 vco/24 1 1 1 0 vco/16 vco/16 vco/16 1 1 1 1 vco/16 vco/16 vco/24 table 2 output frequency selection table (vco_sel1 = 1) inputs outputs vco_sel0 fsela fselb fselc qa(0:4) qb(0:4) qc(0:3) 0 0 0 0 vco/2 vco/2 vco/4 0 0 0 1 vco/2 vco/2 vco/6 0 0 1 0 vco/2 vco/4 vco/4 0 0 1 1 vco/2 vco/4 vco/6 0 1 0 0 vco/4 vco/2 vco/4 0 1 0 1 vco/4 vco/2 vco/6 0 1 1 0 vco/4 vco/4 vco/4 0 1 1 1 vco/4 vco/4 vco/6 1 0 0 0 vco/4 vco/4 vco/8 1 0 0 1 vco/4 vco/4 vco/12 1 0 1 0 vco/4 vco/8 vco/8 1 0 1 1 vco/4 vco/8 vco/12 1 1 0 0 vco/8 vco/4 vco/8 1 1 0 1 vco/8 vco/4 vco/12 1 1 1 0 vco/8 vco/8 vco/8 1 1 1 1 vco/8 vco/8 vco/12 table 3 pin description pin no. pin name i/o description 2 mr# i active low master reset pin. it has a 250k ? internal pull-up. when forced low, all outputs are tri-stated (high impedance) and internal ratio dividers are reset. 3 oe i active high output enable pin. it has a 250k ? internal pull-up. when forced low, qa(0:4), qb(0:4), and qc(0:3) outputs are stopped in a low state. qfb is not effected by this signal. 7,4, 5 fsel(a,b,c) i input select pins for setting the output dividers at qa(0:4), qb(0:4), and qc(0:3) respectively. each pin has an internal 250k ? pull-down. see table 2, page 3. 6 pll_en i input pin for bypassing the pll. it has an internal 250k ? pull-up. when forced low, the input reference clock (applied at tclk0, or tclk1) bypasses the pll and drives the dividers, typically for device testing. in this case, the pll is disabled. 8 tclk_sel i input pin for selecting tclk0 or tclk1 as input reference. when tclk_sel = 0, tclk0 is selected, when tclk_sel = 1, tclk1 is selected. this pin has a 250k ? internal pull-down. 9,10 tclk(0:1) i input pins for applying a reference clock to the pll. the active input is selected by tclk_sel, pin# 8. tclk0 has a 250k ? internal pull-down. tclk1 has a 250k ? internal pull-up. 14, 20 fselfb(0:1) i input select pins for setting the feedback divide ratio at qfb output, pin#29. see table 1, page1. each of these pins has a 250k ? internal pull-down. 25,23,21, 18,16 qa(0:4) o high drive, low voltage cmos, output clock buffers, bank qa. their divide ratio is programmed by fsela, pin#7. 29 qfb o low voltage cmos output feedback clock to the internal pll. the divide ratio for this output is set by fslefb(0:1). a delay capacitor, or trace may be applied to this pin in order to control the input reference/output banks phase relationship. 31 fb_in i feedback input pin. typically connects to the qfb output for accessing the feedback to the pll. it has a 250k ? internal pull-up.
3.3v, 150mhz, multi-output zero delay buffer cypress semiconductor corporation http://www.cypress.com document#: 38- 07091 rev. *b 12/26/2002 page 4 of 8 z9975 pin description (cont.) pin no. pin name i/o description 11 vco_sel1 i output division selection contains an internal pulldown resistor. when left floating or pulled to vss (logic 0) output frequencies are described by output frequency table 2, when driven to vdd (logic 1), output frequencies are described by table 3. 40,38,36, 34,32 qb(0:4) o high drive, low voltage cmos, output clock buffers, bank qb. their divide ratio is programmed by fselb, pin#4. 50,48,46, 44 qc(0:3) o high drive, low voltage cmos, output clock buffers, bank qc. their divide ratio is programmed by fselc, pin#5. 52 vco_sel0 i input select pin for setting the divider of the vco output. it has a 250k ? internal pull-down. if vco_sel = 0, then the pll vco output is divided by 2. if vco_sel = 1, then the pll vco output is divided by 4. see fig.1, page2; table 1, page1, table 2, page 3. 27,42 n/c - these pins are not connected internally. they may be attached to a ground plane. 12 vddi p power for input logic circuitry. 15 vssi p ground for input logic circuitry. 13, vdda p power and ground supply pins for internal analog circuitry. 17,22,26 vdda p 3.3v supply for qa(0:4) output bank, and fselfb1 input. 19,24 vssa p common ground for qa(0:4) output bank, and fselfb1 input. 28, 30 vddfb / vssfb p power and ground supply pins for qfb output and fb_in input pins and digital circuitry. 33,37,41 vddb p 3.3v supply for qb(0:4) output bank. 35,39 vssb p common ground for qb(0:4) output bank. 45,49 vddc p 3.3v supply for qc(0:3) output bank and vco_sel pin. 43,47,51 vssc p common ground for qc(0:3) output bank and vco_sel pin. 1 vssa p analog ground a bypass capacitor (0.1 f) should be placed as close as possible to each positive power pin (<0.2?). if these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductances of the traces. glitch-free output frequency transitions customarily when zero delay buffers have their internal counter?s changed ?on the fly? their output clock periods will: a. contain short or ?runt? clock periods. these are clock cycles in which the cycle(s) are shorter in period than either the old or new frequency that is being transitioned to. b. contain stretched clock periods. these are clock cycles in which the cycle(s) are longer in period than either the old or new frequency that is being transitioned to. this device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic levels of any or all of the following pins changed ?on the fly? while it is operating: fsela, fselb, fselc, vco_sel, fselfb1, and fselfb2.
3.3v, 150mhz, multi-output zero delay buffer cypress semiconductor corporation http://www.cypress.com document#: 38- 07091 rev. *b 12/26/2002 page 5 of 8 z9975 maximum ratings1 input voltage relative to vss: vss-0.3v input voltage relative to vdd: vdd+0.3v storage temperature: -65c to + 150 c operating temperature: -40 c to +85c maximum power supply: 5.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) 3.3v, 150mhz, multi-output zero delay buffer cypress semiconductor corporation http://www.cypress.com document#: 38- 07091 rev. *b 12/26/2002 page 6 of 8 z9975 ac parameters characteristic symbol min typ max units conditions output duty cycle tpw tcycle/2 - 800 tcycle/2 + 500 tcycle/2 + 800 ps measured @ vdd/2 rise time / fall time t r, t f 0.15 - 1.5 ns measured between 0.8v and 2.0v output impedance z o 710 ? output to output skew t s - - 250 ps all output equally loaded propagation delay, tclk(0:1) to fbin t pd -250 - 100 ps measured for 50mhz at vdd/2 cycle to cycle jitter tj - +100 - ps measured for 50 mhz at vdd/2 output disable time tplz, tphz 2 - 10 ns after mr# goes low output enable time tpzl 2 - 10 ns after mr# goes high - - 150 q ( 2) - - 125 q ( 4) maximum output frequency fout --83 mhz q ( 6) vdd* = 3.3v + 5%, ta = -40 c to +85 c note: parameters are guaranteed by design and characterization. not 100% tested in production. all parameters specified with loaded outputs. z9975 outputs can drive series or parallel terminator 50 ? (or 50 ? to vdd/2). test circuit diagram note: all buffer outputs are tied to a common 3.3 volt vdd (vdd*) for testing purposes probe vdd* impedance 7 ? ? ? ? ? output under test 43 50 1k 1k
3.3v, 150mhz, multi-output zero delay buffer cypress semiconductor corporation http://www.cypress.com document#: 38- 07091 rev. *b 12/26/2002 page 7 of 8 z9975 package drawing and dimensions (52 tqfp) 52 pin tqfp outline dimensions inches millimeters symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a2 0.037 - 0.041 0.95 - 1.05 d - 0.472 - - 12.00 - d 1 - 0.394 - - 10.00 - b 0.009 - 0.015 0.22 - 0.38 e 0.026 bsc 0.65 bsc l 0.018 - 0.030 0.45 - 0.75 ordering information part number package type production flow z9975ca 52 tqfp industrial, -40 c to +85 c note: the ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. marking: example: cypress z9975ca date code, lot # z9975ca package a = tqfp revision imi device number notice cypress semiconductor corporation reserves the right to make changes to its products in order to improve design, performance or reliability. cypress semiconductor corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by cypress semiconductor corporation for the use of its products in the life supporting and medical applications. d d 1 a 2 b e 10 a l a 1
3.3v, 150mhz, multi-output zero delay buffer cypress semiconductor corporation http://www.cypress.com document#: 38- 07091 rev. *b 12/26/2002 page 8 of 8 z9975 document title: z9975 3.3v, 150 mhz multi-output zero delay buffer document number: 38-07091 rev. ecn no. issue date orig. of change description of change ** 107127 06/05/01 ika converted from imi to cypress *a 108069 07/03/01 ndp changed commercial to industrial *b 122776 12/26/02 rbi add power up requirements to maximum ratings information.
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